1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a memory device compatible with a static random access memory, which employs dynamic random access memory cells.
2. Description of the Related Art
Generally, random access memory (RAM) devices are classified into static RAM (SRAM) devices and dynamic RAM (DRAM) devices. A RAM device generally includes a memory array composed of a plurality of unit memory cells arranged in a matrix form defined by rows and columns, and peripheral circuits used to control the input/output of data to/from the unit memory cells. Each of the unit memory cells stores one bit of data. In an SRAM, each unit memory cell is implemented using four transistors that form a latch structure and two transistors that act as transmission gates. Since SRAM devices store data in unit memory cells having latch structures, no refresh operation is required to maintain the stored data. Further, the SRAM devices have the advantages of a fast operating speed and low power consumption compared to DRAM devices.
However, since each unit memory cell of an SRAM is composed of six transistors, the SRAM is disadvantageous in that it requires a large wafer area compared to a DRAM that generally has unit memory cells each implemented using a transistor and a capacitor. In more detail, in order to manufacture a semiconductor memory device of the same capacity, the SRAM requires a wafer about six to ten times larger than that of the DRAM. The necessity of such a large wafer increases the unit cost of the SRAM. When a DRAM instead of an SRAM is used to reduce the cost, a DRAM controller is additionally required to perform a periodic refresh operation. Further, the entire performance of a system deteriorates due to the time required to perform the refresh operation and a slow operating speed.
In order to overcome the disadvantages of the DRAM and the SRAM, attempts have been made to implement an SRAM to which DRAM memory cells are applied. One of these attempts is the technology of effectively concealing a refresh operation from the outside of the memory to enable the memory to be compatible with the SRAM.
In a read-access operation based on the conventional SRAM-compatible technology, an additional time period is required for internal refresh operation within a read-access interval, or read-access timing is delayed in order to obtain a time required to refresh DRAM cells of a memory array.
However, such a conventional synchronous SRAM-compatible memory is problematic in that the memory read-access timing is internally delayed, and an overall read operating speed is decreased due to the delay of the access timing.